1. Field of the Invention
The invention relates generally to RAID controller architecture and in particular to a hierarchical memory interface which provides high bandwidth for RAID data transfers while permitting easy scalability to support slower "legacy" RAID controller software.
2. Related Patents
This patent is related to commonly assigned, co-pending, U.S. Pat. No. 5,634,033, filed Dec. 16, 1994 by Stewart et al., entitled (as amended) DISK ARRAY STORAGE SYSTEM ARCHITECTURE FOR PARITY OPERATIONS SIMULTANEOUS WITH OTHER DATA OPERATIONS, which is hereby incorporated by reference.
This patent is related to commonly assigned, co-pending, U.S. patent application Ser. No. 08/674,592, filed Jun. 28, 1996 by Corrigan et al. entitled INTER-BUS BRIDGE CIRCUIT WITH INTEGRATED MEMORY PORT, which is hereby incorporated by reference.
3. Discussion of Related Art
Modern mass storage subsystems are continuing to provide increasing storage capacities to fulfill user demands from host computer system applications. Due to this critical reliance on large capacity mass storage, demands for enhanced reliability are also high. Various storage device configurations and geometries are commonly applied to meet the demands for higher storage capacity while maintaining or enhancing reliability of the mass storage subsystems.
A popular solution to these mass storage demands for increased capacity and reliability is the use of multiple smaller storage modules configured in geometries that permit redundancy of stored data to assure data integrity in case of various failures. In many such redundant subsystems, recovery from many common failures is automated within the storage subsystem itself due to the use of data redundancy, error codes, and so-called "hot spares" (extra storage modules which may be activated to replace a failed, previously active storage module). These subsystems are typically referred to as redundant arrays of inexpensive (or independent) disks (or more commonly by the acronym RAID). The 1987 publication by David A. Patterson, et al., from University of California at Berkeley entitled A Case for Redundant Arrays of Inexpensive Disks (RAID), reviews the fundamental concepts of RAID technology.
There are five "levels" of standard geometries defined in the Patterson publication. The simplest array, a RAID level 1 system, comprises one or more disks for storing data and an equal number of additional mirror disks for storing copies of the information written to the data disks. The remaining RAID levels, identified as RAID level 2,3,4 and 5 systems, segment the data into portions for storage across several data disks. One of more additional disks are utilized to store error check or parity information. A single unit of storage is spread across the several disk drives and is commonly referred to as a "stripe." The stripe consists of the related data written in each of the disk drive containing data plus the parity (error recovery) information written to the parity disk drive.
RAID storage subsystems typically utilize a control module that shields the user or host system from the details of managing the redundant array. The controller makes the subsystem appear to the host computer as a single, highly reliable, high capacity disk drive. In fact, the RAID controller may distribute the host computer system supplied data across a plurality of the small independent drives with redundancy and error checking information so as to improve subsystem performance and reliability. Frequently RAID subsystems provide large cache memory structures to further improve the performance of the RAID subsystem. The cache memory is associated with the control module such that the storage blocks on the disk array are mapped to blocks in the cache. This mapping is also transparent to the host system. The host system simply requests blocks of data to be read or written and the RAID controller manipulates the disk array and cache memory as required.
Processing of I/O requests generated by a host computers requires significant data bandwidth transferring data to and from the cache memory. For example, data read from the disk array of the RAID storage subsystem into the cache memory may be transferred to a requesting host computer system to satisfy a read I/O request. Other data may be received from a host computer system and transferred to the cache memory to satisfy a write I/O request. Simultaneous with such host initiated transfers of data, background operations performed by the RAID controller of the RAID storage subsystem may post data in the cache memory to the drive array or read data from the disk array to the cache memory. All these exemplary data transfer operations between a host computer and the cache memory and between the disk array and the cache memory require a portion of the total available bandwidth on the bus to the cache memory.
As higher performance host computer connections have developed for connecting RAID storage subsystems to host computer systems, the data transfer bandwidth of the RAID cache memory subsystem has become a performance bottleneck. However, changing the architecture of the cache memory subsystem in the evolutionary design of RAID controllers can create problems in supporting older RAID controller software structures. The investment in older RAID controller software can be significant such that it is highly desirable to port the older control software up to newer RAID controller designs. Old system designs which require support (backward compatibility) in newer controller designs are often referred to as "legacy" systems.
If a RAID subsystem design engineer creates a new cache memory architecture to improve overall RAID performance, older legacy system control software and structures may be abandoned due to fundamental changes in the structure of, operation of, and interface to, the new cache memory subsystem. Redesign of the legacy system control algorithms and structures can add significant costs, complexity, and delay to the development and marketing of new RAID controller systems.
It is evident from the above discussion that an improved architecture for RAID controller cache memory design is required to improve performance of the cache memory subsystem while maintaining compatibility with legacy systems.